Memory Controller For Heterogeneous Configurable Integrated Circuit

ABSTRACT

A system including a configurable memory controller, a memory interface, and a configurable high speed communications fabric comprising a plurality of interconnect stations arranged in an array and operable to implement a plurality of pipelined buses, where the configurable memory controller is operably coupled to the configurable high speed communications fabric using a first interconnect station of the plurality of interconnect stations, where the memory interface is operably coupled to the configurable high speed communications fabric using a second interconnect station of the plurality of interconnect stations, where the plurality of interconnect stations are configured to satisfy a timing requirement of the memory interface, and where the configurable memory controller, the memory interface, and the configurable high speed communications fabric are associated with a configurable integrated circuit.

PRIORITY

This application is a divisional application of U.S. patent applicationSer. No. 14,/729,829, filed on Jun. 3, 2015 and entitled in the samename and inventor of “Memory Controller for Heterogeneous ConfigurableIntegrated Circuit,” which is a divisional application of U.S. patentapplication Ser. No. 11/855,740, filed on Sep. 14, 2007 and entitled inthe same name and inventor of “Memory Controller for HeterogeneousConfigurable Integrated Circuit,” which are hereby incorporated byreference in their entireties.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application contains subject matter that may be related tothe subject matter in U.S. application Ser. No. 11/901,182, issued asU.S. Pat. No. 7,902, 862, entitled: “High-Bandwidth Interconnect Networkfor an Integrated Circuit”, filed on Sep. 14, 2007, and assigned to theassignee of the present application.

The present application also contains subject matter that may be relatedto the subject matter in U.S. application Ser. No. 11/855,666, issued asU.S. Pat. No. 7,557,605, entitled: “Heterogeneous ConfigurableIntegrated Circuit” , filed on Sep. 14, 2007, and assigned to theassignee of the present invention.

The present application also contains subject matter that may be relatedto the subject matter in U.S. application Ser. No.11/855, 697, issued asU.S. Pat. No. 7,773,595, entitled: “System and Method for ParsingFrames” , filed on Sep. 14, 2007, and assigned to the assignee of thepresent invention.

The present application also contains subject matter that may be relatedto the subject matter in U.S. application Ser. No. 11/855,721, issued asU.S. Pat. No. 7,889,530, entitled: “Reconfigurable Content-AddressableMemory”, filed on Sep. 14, 2007, and assigned to the assignee of thepresent invention.

The present application also contains subject matter that may be relatedto the subject matter in U.S. application Ser. No. 11/855,761, issued asU.S. Pat. No. 8,049,531, entitled: “General Purpose Input/Output Systemand Method”, filed on Sep. 14, 2007, and assigned to the assignee of thepresent invention.

All mentioned U.S. applications are hereby incorporated by reference.

BACKGROUND

Digital systems can be implemented using off-the-shelf integratedcircuits. However, system designers can often reduce cost, increaseperformance, or add capabilities by employing in the system someintegrated circuits whose logic functions can be customized. Two commonkinds of customizable integrated circuits in digital systems areapplication-specific integrated circuits (ASICs) and field-programmablegate arrays (FPGAs).

ASICs are designed and manufactured for a particular application. AnASIC includes circuits selected from a library of small logic cells. Atypical ASIC also includes large special-purpose blocks that implementwidely-used functions, such as a multi-kilobit random-access memory(RAM) or a microprocessor. The logic cells and special-function blocksmust be placed at suitable locations on the ASIC and connected by meansof wiring.

Application-specific integrated circuits (ASICs) have severaladvantages. As an ASIC contains only the circuits required for theapplication, it has a small die size. An ASIC also has low powerconsumption and high performance. However, ASICs have somedisadvantages. It takes a lot of time and money to design ASICs becausethe design process is complex. Creating prototypes for an ASIC iscomplex as well, so prototyping also takes a lot of time and money.

Field-programmable gate arrays (FPGAs) are another kind of customizableintegrated circuit that is common in digital systems. An FPGA isgeneral-purpose device. It is meant to be configured for a particularapplication by the system designer.

Field-programmable gate arrays (FPGAs) have advantages overapplication-specific integrated circuits (ASICs). Prototyping an FPGA isa relatively fast and inexpensive process. Also, it takes less time andmoney to implement a design in an FPGA than to design an ASIC becausethe FPGA design process has fewer steps.

FPGAs have some disadvantages, the most important being die area. Logicblocks require more area than the equivalent ASIC logic cells, and theswitches and configuration memory bits in routing crossbars (XBARs)require far more area than the equivalent wiring of an ASIC. FPGAs alsohave higher power consumption and lower performance than ASICs.

SUMMARY

In general, in one aspect, the invention is related to a system. Thesystem including a configurable memory controller, a memory interface,and a configurable high speed communications fabric comprising aplurality of interconnect stations arranged in an array and operable toimplement a plurality of pipelined buses, where the configurable memorycontroller is operably coupled to the configurable high speedcommunications fabric using a first interconnect station of theplurality of interconnect stations, where the memory interface isoperably coupled to the configurable high speed communications fabricusing a second interconnect station of the plurality of interconnectstations, where the plurality of interconnect stations are configured tosatisfy a timing requirement of the memory interface, and where theconfigurable memory controller, the memory interface, and theconfigurable high speed communications fabric are associated with aconfigurable integrated circuit.

In general, in one aspect, the invention relates to a method forimplementing a design using a configurable integrated circuit includinga programmable logic block (PLB), a configurable memory controller, anda plurality of interconnect stations. The method including mapping thedesign to use the PLB and the configurable memory controller,identifying a plurality of signal nodes associated with at least oneselected from the group consisting of the PLB and the configurablememory controller, and configuring the plurality of interconnectstations to connect the plurality of signal nodes, wherein configuringthe plurality of interconnect stations comprises bypassing a pipelineregister of at least one of the plurality of interconnect stations.

In general, in one aspect, the invention relates to a computer readablemedium storing instructions for implementing a design using aconfigurable integrated circuit including a programmable logic block(PLB), a reconfigurable memory controller, and a plurality ofinterconnect stations. The instructions including functionality to mapthe design to use the PLB and the configurable memory controller;identify a plurality of signal nodes associated with at least oneselected from the group consisting of the PLB and the configurablememory controller; and configure the plurality of interconnect stationsto connect the plurality of signal nodes, where configuring theplurality of interconnect stations comprises bypassing a pipelineregister of at least one of the plurality of interconnect stations.

Other aspects of the invention will be apparent from the followingdescription and the appended claims.

BRIEF SUMMARY OF THE DRAWINGS

FIG. 1 shows an FPGA in accordance with one or more embodiments of theinvention.

FIG. 2 shows a heterogeneous configurable integrated circuit inaccordance with one or more embodiments of the invention.

FIG. 3A and 3B show an inter-mesh of interconnect stations and logicblocks in accordance with one or more embodiments of the invention.

FIG. 4 shows a memory controller interfacing with a general purposeinput/output (GPIO) and a user logic in accordance with one or moreembodiments of the invention.

FIG. 5 shows an Address/Control path and Data path in accordance withone or more embodiments of the present invention.

FIG. 6 shows Write/Read FIFO operations in accordance with one or moreembodiments of the invention.

FIG. 7 shows configuration register and configuration bit interactionswith the state machine in accordance with one or more embodiments of theinvention.

FIG. 8 shows an exemplary design and programming system for theheterogeneous configurable integrated circuit in accordance with one ormore embodiments of the invention.

DETAILED DESCRIPTION

An example of the invention will now be described in detail withreference to the accompanying figures. Like elements in the variousfigures are denoted by like reference numerals for consistency. Further,the use of “ST” in the drawings is equivalent to the use of “Step” inthe detailed description below.

In examples of the invention, numerous specific details are set forth inorder to provide a more thorough understanding of the invention.However, it will be apparent to one of ordinary skill in the art thatthe invention may be practiced without these specific details. In otherinstances, well-known features have not been described in detail toavoid unnecessarily complicating the description.

In general, in one aspect, the invention relates to a memory controllerfor a heterogeneous configurable integrated circuit and the associateddesign method. In one or more embodiments of the invention, the memorycontroller is connected to PLBs and other special-purpose blocks in anFPGA using pipelined buses forming a reconfigurable high speedcommunications fabric. This communications fabric improves the operatingspeed and narrows the performance gap between the FPGA and an ASIC. Thehigh speed communications fabric, however, introduces interconnectionlatency due to the inherent nature of the pipelined buses. Certaincircuit configurations are required to accommodate the latency forproper operation of the FPGA. For example, in the memory controller anda special-purpose block performing general purpose input/output (GPIO)functions, circuit configurations are devised to accommodate the latencyand take advantage of the high speed communications fabric forconnecting PLBs, the memory controller, and the GPIO block in the FPGA.

FIG. 1 shows an FPGA (199) in accordance with one or more embodiments ofthe invention. As shown in FIG. 1, the FPGA (199) includes one or moreprogrammable logic blocks (101), one or more configurablespecial-purpose blocks (151, 155), and one or more routing crossbars(XBARs) (100, 125, 130, 131, 132, 133). Each programmable logic block(101) may include one or more 4-input lookup tables (LUTs) (not shown)and one or more configurable 1-bit sequential cells (not shown). Aconfigurable special-purpose block (151, 155) implements a widely-usedfunction. Those skilled in the art, having the benefit of this detaileddescription, will appreciate the FPGA (199) may have more than one typeof special-purpose block (151, 155).

As also shown in FIG. 1, the routing crossbars (XBARs) (100, 125, 130,131, 132, 133) form a two-dimensional routing network that providesconfigurable connections among the logic blocks (101) and thespecial-purpose blocks (151, 155). Each XBAR may be connected to thenearest-neighbor XBARs in four directions and to either a logic block ora special-purpose block. For example, routing crossbar (125) and routingcrossbar (100) are connected by buses (104). Although both logic blocksand special-purpose blocks connect to XBARS, special-purpose blocks aretypically much larger than logic blocks and typically have more inputand output signals. Accordingly, a special-purpose block may beconnected by a plurality of buses to a plurality of XBARs (e.g.,special-purpose block (151) is connected to XBARs (130, 131, 132, 133)).

The logic blocks (101), special-purpose blocks (151, 155), and routingcrossbars (100, 125, 130, 131, 132, 133) may contain configurationmemory bits. A user's design is implemented in the FPGA by setting theconfiguration memory bits appropriately. Several forms of configurationmemory are used by contemporary FPGAs, the most common form being staticrandom-access memory (SRAM).

FIG. 2 shows part of a heterogeneous configurable integrated circuit(HCIC) (200) in accordance with one or more embodiments of theinvention. As shown in FIG. 2, the HCIC (200) has numerous componentsincluding one or more columns of GPIO blocks (205, 210), at least onecolumn of single port ram units (SPRAM) (215), multiple columns of PLBs(220), at least one column of special-purpose blocks (225), at least onecolumn of dual port RAM units (DPRAM) (230), multiple columns ofstations (235, 240, 245, 250), and multiple quad MAC/PCS/SERDES units(255, 260, 265) bordering the HCIC (200). In one or more embodiments ofthe invention, the HCIC (200) is fabricated on a monolithicsemiconductor substrate.

Although FIG. 2 only shows quad MAC/PCS/SERDES units (255, 260, 265)bordering one side of the HCIC (200), those skilled in the art, havingthe benefit of this detailed description, will appreciate otherembodiments of the invention include quad MAC/PCS/SERDES units onmultiple sides of the HCIC (200). Additionally, although FIG. 2 onlyshows a single column of SPRAM units (215), two columns of PLBs (220),and a single column of DPRAM units (230), those skilled in the art,having the benefit of this detailed description, will also appreciatethe HCIC (220) may have any number of columns of the mentionedcomponents.

In one or more embodiments of the invention, a special-purpose block(225) is a reconfigurable frame parser unit, a reconfigurable arithmeticunit (RAU), a reconfigurable content addressable memories (RCAM), amemory controller, etc. Although FIG. 2 only shows a single column ofspecial-purpose blocks (225), those skilled in the art, having thebenefit of this detailed description, will also appreciate otherembodiments of the invention have multiple columns of special-purposeblocks, where each column contains a single type of special-purposeblock (i.e., RCAM, RAU, etc.).

In one or more embodiments of the invention, the multiple stations (235,240, 245, 250) form a data cross-connect (DCC) network. This DCC networkis a two-dimensional grid of stations that spans the entire HCIC (200).In one or more embodiments of the invention, the DCC network is asdescribed in U.S. application Ser. No. 11/901,182, issued as U.S. Pat.No. 7,902,862, entitled “High-Bandwidth Interconnect Network for anIntegrated Circuit,” which was previously incorporated by reference. Inone or more embodiments of the invention, the HCIC (200) also includes arouting crossbar network (not shown) in a plane parallel to the DCCnetwork.

FIG. 3A shows an inter-mesh of interconnect stations and logic blocks inaccordance with an embodiment of the present invention. Here, an arrayof interconnect stations (denoted with an ‘S’ in FIG. 3A and FIG. 3B)are intermeshed with an array of PLBs (denoted as ‘PLB’ in FIG. 3A andFIG. 3B). The array of interconnect stations implements pipelined busesto form a high speed communications fabric. The array of PLBs forms aPLB fabric to perform general functions as needed. In addition to thePLBs, logic blocks also include special-purpose block to performdedicated special functions. In one example, a special-purpose block maybe implemented as a mask programmable block, or hard macro, (301)connecting to neighboring interconnect stations. In another example, thespecial-purpose block may be implemented using a collection of PLBs(302304) as a soft macro. The soft macro may be configured to performthe specific function of the special-purpose block by way of a netlistor a hardware description language such as Verilog, VHDL, or the like.In one example, each interconnect station includes bus connections toeach neighboring PLBs, referred to herein as ports, and bus connectionsto each neighboring interconnect stations, referred to herein as ramps.In an example, for each direction, north, south, east, and west, thereare four input ramps and four output ramps to other interconnectstations. Each ramp is five bits wide. On each interconnect stationthere are four input ports and four output ports. Each port connectingthe interconnect station to the PLBs is five bits wide. The ports act asentry and exit to and from the high speed communications fabric. In someexamples, the signal propagation delay between consecutive interconnectstations may be represented by T and the pipelined buses may be clockedup to the maximum frequency f=1/T. There may be slight time increase fordelay through each of the pipeline register. However this increase maybe small compared to T. The heterogeneous configurable integratedcircuit using pipelined buses for connecting PLBs and special-purposeblocks may be as described in U.S. application Ser. No. 11/855,666entitled “Heterogeneous Configurable Integrated Circuit,” which waspreviously incorporated by reference.

As discussed above, one or more of the special-purpose blocks (225) maybe a memory-controller. In one example, the memory controller (499) isimplemented as the hard macro (301). A first signal propagates along afirst signal path (304, 311-317), and (301). A second signal propagatesalong a second signal path (302, 323, 324, and 301). The first andsecond signals may be address input signals generated from PLBs(302-304). In another example, the hard macro (301) may include aplurality of the GPIO blocks. The first and second signals may be datainput signals generated from PLBs (302-304). In both examples, the PLBs(302-304) may be part of a soft macro. Based on the circuit operation,excessive propagation delays along the first and second signal paths maynegatively impact the operation or performance of the memory controlleror the plurality of the GPIO blocks. The negative impact may bereflected in reduced operating frequency or decreased data connectionbandwidth. The interconnect stations along the first and second signalpaths may act as pipelined sequential registers and allow the first andsecond signals to be clocked at increased frequency thus increasing thedata connection bandwidth. However, interconnection latency may beintroduced due to the inherent nature of the pipelined buses. Theinterconnection latency may vary depending on the distance a signaltravels between the source and destination. In the above example, byusing the pipelined connection, an interconnection latency of sevenclock cycles may be introduced along the first signal path as the firstsignal traverses the pipeline registers of the interconnect stations(311-317). An interconnection latency of two clock cycles may beintroduced along the second signal path as the second signal traversesthe pipeline registers of the interconnect stations (323 and 324). Thismismatch in interconnection latency may not be acceptable according tothe circuit operation of the memory controller or the plurality of theGPIO blocks. One approach to eliminate this interconnection latencymismatch is shown in FIG. 3B. Here, the signal path (304, 317, 301) andsignal path (302, 324, 301) are matched in interconnection latency byoptimizing the physical placements of the memory controller, or theplurality of the GPIO blocks, and the designation of the PLBs. However,the strong placement constraint demanded by this approach may not befeasible in the case where multiple interconnection latency requirementsmay impose conflicting placement constraints. For an example, the memorycontroller, or the plurality of the GPIO blocks, may include 50 or moreaddress or data input signals which may all require matchedinterconnection latency. One skilled in the art will recognize that itmay not be feasible to satisfy the interconnect latency matchingrequirement from such large number of signal paths. A second approach isshown in FIG. 3A where the interconnect latency may be adjusted for eachsignal path according to the matching requirement. Here, interconnectstations (312) and (314) along the first signal path are configured asregistered interconnect stations. The interconnect stations (313) and(315-317) are configured to have their pipeline registers bypassed. Theinterconnect latency along the first signal path may be matched to thatof the second signal path in this manner. In this example, the resultantinterconnect latency is two clock cycles limited by the second signalpath which is the shorter of the two signal paths that requireinterconnect latency matching. The resultant maximum frequency that thefirst and second signal paths may be clocked is f/3 limited by thepipeline stages (315317) of the first signal path with a total delay of3T. In an example where circuit operation requires to match theinterconnect latency for multiple signals along respective signal paths,the minimum number of clock cycles of the resultant interconnect latencymay be determined according to the shortest signal path and theresultant maximum frequency that these multiple signal paths can beclocked may be determined according to the longest signal path. Abenefit function may be formulated representing weighed impact on systemperformance from an estimate of the interconnection latency and anestimate of the clock frequency of the multiple signal paths. Thebenefit function may be used to drive the placement or routingalgorithms for implementing a design using the memory controller, or theplurality of the GPIO blocks, in the heterogeneous configurableintegrated circuit.

Although the many examples above are shown using the memory controller,or the plurality of the GPIO blocks, implemented as a hard macro, oneskilled in the art will appreciate that the invention may be practicedwhere the memory controller, or the plurality of the GPIO blocks, isimplemented as a soft macro and achieve similar advantageous results.

FIG. 4 shows the memory controller (499) interfacing a GPIO and a userlogic in accordance with one or more embodiments of the invention. Here,user logic (402) exchanges signals (such as the mode register data bus(414), AF_DATA[58:0], START_INIT, INIT_DONE, BYPASS, SYS_CLK, etc) withthe memory controller (499), the memory controller (499) exchangessignals (such as RX_PUSH, TX_POP, ADDRICMD, etc.) with the GPIO, and theGPIO exchanges signals (such as TX_DATA[63:0], R_DATA[71:0], etc.) withthe user logic (402). The GPIO includes the digital GPIO (404) and theanalog GPIO (406). Three FIFOs, including the write FIFO (408), the readFIFO (410), and the address FIFO (412), may be provided for holdinginformation related to the write, read, and address operations,respectively. Among the three FIFOs, the read FIFO (410) and the writeFIFO (408) may be implemented in the digital GPIO (404), and the addressFIFO (412) may be implemented in the memory controller (499) as shown inFIG. 4. The digital GPIO (404) and the analog GPIO (406) includemultiple digital GPIO blocks and multiple analog GPIO blocksrespectively (not shown). A digital GPIO block and an analog GPIO blockforms a GPIO block (not shown) which includes circuits associated withone or two bit of data. Although the block diagram of FIG. 4 shows thedigital GPIO (404) separate from the analog GPIO (406) withoutillustrating multiple GPIO blocks, in embodiments of the invention, eachGPIO block may be implemented as a hard macro and multiple GPIO blocksmay be disposed side by side to form the GPIO (212) along one or moreedge of a monolithic semiconductor substrate as sown in FIG. 2B.

The memory controller (499) may be used to schedule read and writetransactions with an array of external memory devices (not shown). Theexternal memory devices may be of different flavors of synchronousdynamic random access memory (SDRAM) such as double data rate (DDR),DDR2, DDR3, quad data rate (QDR), QDR II, and QDR II+SDRAMs, as well asreduced latency DRAM (RLDRAM), and RLDRAM II.

These read and write transactions may be tracked with an address FIFO(412). The memory controller (499) may also be used for initialization,for providing a debugging bypass mode and for other specialized userrequirements. The mode register data bus (414) (such as REG_ADDR,REG_DATA, REG RDATA, etc.) is used for setting values in the modeconfiguration registers (415). The configuration bits from theconfiguration registers (415) indicate to the memory controller (499)regarding the memory types, address, data width, and operatingfrequency. The delay calibration block (416) included in the digitalGPIO block (404), in accordance with an embodiment of present invention,is used to determine the offset required to center data (such asDATA[63:0]) with respect to a strobe (such as DQS[p,n][17:0]) to meetcircuit requirement, such as data sampling margins. The delaycalibration block may also be used to compensate for jitter,board-induced skews, and other known variations that impact the relativesignal timings such as process variation, voltage variation, andtemperature variation.

In one or more embodiments of the invention, clocking data into and outof the external memory uses a clock that may be out of phase with aclock signal generated by the memory controller (as specified byconfiguration bits in configuration registers (415). These two clockdomains may be referred to as mesochronous clocking domains. Theclocking FIFOs provided at the memory controller interface are intendedto provide clock alignment for the mesochronous clocking domains so thatdata can be written to or retrieved correctly from external memory.

A state machine (not shown) may be provided for sequencing commands andmanaging the timing relationships between the commands for the read andwrite transactions. The state machine is configurable based on thememory type settings in the configuration registers (415). Theaddresses, data, control, and clock signals (such as ADDR[22:0],DATA[63:0], DQS[p,n][17:0], RAS#, CAS#, WE#IW#, CKE[3:0] etc.) of theanalog GPIO (406) constitute the physical interfaces to the externalmemory device (not shown). The ECC block (420), provided within thedigital GPIO block (404) in this exemplary configuration, provides errordetection and correction capabilities. Although FIG. 4 shows only onememory controller, more than one memory controllers may be instantiated,and wider buses can be accordingly implemented.

More details of the signals shown in FIG. 4 are listed in the followingTable 1.

TABLE 1 Memory controller user interface signals. Signal DescriptionUSER −> MEMORY CONTROLLER AF_DATA[58:0] Address FIFO data containinginformation such as row address, column address, etc., (contains writeaddress for QDR). See Section 4.3.1 for details AF_VALID Address validsignal BYPASS When this bit is set to 1, the memory controller justpasses through all commands on the AF DATA bus. TX PUSH Signal from theuser logic to indicate that data is being written into the write FIFO RXPOP Signal from the user logic to indicate that data is being pulled outof the Read FIFO RESET Global reset for the controller START_INIT Beginmemory initialization REG_ADDR[7:0] Address bits for memory controllerregisters REG WDATA[7:0] Write Data bits for memory controller registersREG RDATA[7:0] Read Data bits for memory controller registers REG WERead/Write bit for the register interface. If set to 0, data from theaddress specified on REG ADDR is available on the REG RDATA bus to theuser. When set to 1, user data on the REG WDATA bus is written into theregister specified by REG ADDR REFRESH Signal from the user to instructthe memory controller to issue a refresh on demand AUTO REFRESH(Register When this bit is set to 1, the memory bit) controller willissue refreshes to the external memory device automatically POWER DOWN(Register When this bit is set to 1, the memory controller Bit) willmanage power, in a limited way, on the external memory deviceautomatically PRECHARGE When this bit is set to 0, the memory controllerkeeps the bank and row open for subsequent accesses even if the FIFO isempty or it is the last transaction. When set to 1, it automaticallyissues a precharge if the FIFO is empty or after the last transaction LDMODE When set to 1 the controller loads the mode register settings intothe external memory device MEMORY CONTROLLER --> USER AF_ALMOST_FULLAddress FIFO status flag indicating that there is room for one moreaddress AF_EMPTY Address FIFO empty status AF_FULL Address FIFO fullstatus flag TX_FIFO_EMPTY Write FIFO empty status to user TX_FIFO_FULLWrite FIFO full status flag to user TX_FIFO_ALMOST_EMPTY Write FIFOstatus flag to user indicating that no writes will not proceed unlessuser pushes more data RX_FIFO_EMPTY Write FIFO empty status userRX_FIFO_FULL Write FIFO full status flag to user RX_FIFO_ALMOST_FULLRead FIFO status flag to user indicating that reads will not proceedunless the user pops out more data INIT_DONE Status flag indicatingcontroller initiated memory initialization is complete _ECC ERR DET_(—)Status bit indicating that an ECC error was detected ECC ERR CORR Statusbit indicating that an ECC error was corrected MRS_DONE Status flagindicating controller has completed loading the MRS settings into theexternal memory MEMORY CONTROLLER --> GPIOs RXPOP Signal from the userto pop data from the read FIFO onto the data bus TX PUSH Signal from theuser to push data from the data bus into the Write FIFO TX POP Signalfrom the controller to pop data from the write FIFO onto the data busRX_PUSH Signal from the controller to push data from the data bus intothe Read FIFO USER 4 GPIOs TX DATA[63:0] Write FIFO data. This datawidth supports 64-bit wide implementations. (64-data + 8 Data Mask + 8Check Bits) R_DATA[71:0] Read FIFO data. This data width supports 64-bitwide implementations. (64-data + 8 Check Bits) GPIO <−4 EXTERNALMEMORIES DQ Data bits [71:0] DQS Data Strobe [8:0][p, n] DM Data Maskbits [8:0] CB ECC Check Bits [7:0] CLOCK FABRIC 4 GPIOs tx elk TransmitFIFO clock rx clk Receive FIFO clock Sclk Memory Controller Clock GPIOs4 MEMORY CONTROLLER ECC_ERR_DET Status bit indicating that an ECC errorwas detected ECC_ERR_CORK Status bit indicating that an ECC error wascorrected

FIG. 5 shows more details of FIG. 4 and shows the general flow ofinformation in the address/control and data path. In the example here,address FIFO (412), decode logic (501), and address/control circuit(502) are implemented inside the memory controller (499). The read FIFO(410) and write FIFO (408) are implemented inside the GPIO. The addresspins (503), control pins (504), and data pins (505) are physicalinterfaces with the external memory devices and are also implementedinside the GPIO. The tri-state signals (508) control signal directionsof address pins (503), control pins (504), and data pins (505). It isknown in the art that various flavors of SDRAM exhibit a “read latency”and a “write latency” where several clock cycles are required for datato be read from or written to the SDRAM after the address is presented.The read FIFO (410), write FIFO (408), and address FIFO (412) arecontrolled by the memory controller (499) to allow the latent data to besynchronized with the address according to the read/write latency of thevarious flavors of SDRAM. In some examples, the physical size of theread FIFO (410) and write FIFO (408) may be substantial given the largenumber of data pins supported by the memory controller (499).

It may be advantageous to decouple the data path functions (such as theread FIFO (410) and write FIFO (408)) from the memory controller (499).In some examples, the application of the heterogeneous configurableintegrated circuit may not require a memory controller to be configuredand the read FIFO (410) and write FIFO (408) may be configured toperform other functionalities separate from the memory controller.

Various flavors of SDRAM requires different number and order of addresssignals. It is necessary to map address signals (such as AF_DATA[55:0])from the user logic (402) according to the specific number and orderrequired by the external memory devices. This mapping may be performedfrom AF_DATA to Address FIFO (412). Examples of such bit mapping areshown in Table 5, where grey shaded boxes indicate unused bits for thatmemory configuration. In some examples, the memory controller will wrapaddresses back to zero when the top of the memory is reached. The memorycontroller may be configured to automatically handle the variations indensities of the external memory device and the corresponding variationsin boundaries of the row, column address, rank, and bank bits.

FIG. 6 shows basic operations of the write FIFO (408) (TX FIFO) and theread FIFO (410) (RX FIFO) in accordance with an embodiment of thepresent invention. In an example of a write operation, the write FIFO(408) supplies data to be written to the external memory devices usingclock signal (603). The write latency of the external memory devicesdetermines the rate the data in the write FIFO (408) are consumed.Accordingly, the user logic (402) checks TX_FIFO_EMPTY, TX_FIFO_FULL,and TX_FIFO_ALMOST_FULL flags to determine if the write FIFO (408) isready to accept additional data. If TX_FIFO_FULL is asserted, there isno room in the write FIFO (408) to accept additional data. IfTX_FIFO_ALMOST_FULL or TX_FIFO_EMPTY is asserted, the write FIFO (408)can accept additional data such as one or more programmed burst lengthof data. The write FIFO (408) receives data using the clock (605). Thecorresponding write address can be loaded into the address FIFO at anappropriate clock cycle relative to the write FIFO (408) accepting theadditional data according to the write latency of the external memorydevices. Data may be loaded into the write FIFO (408) using TX_PUSHcommand for the programmed burst length. Data is presented to the writeFIFO (408) on TX_DATA_IN. The memory controller monitors the TX_PUSHsignal to manage the PUSH pointer for the TX FIFO internally. Dependingon the content of the write FIFO (408), TX FIFO EMPTY, TX FIFO FULL, orTX FIFO ALMOST FULL may be flagged. The user logic (402) also monitorsthe AF_FIFO_EMPTY, AF FIFO FULL, and AF FIFO ALMOST FULL flags and loadsthe write address into the address FIFO (412). The memory controller(499) monitors the AF VALID signal to manage the PUSH pointer for theaddress FIFO (412) internally, and may flag AF_FIFO_EMPTY, AF_FIFO_FULL,or AF_FIFO_ALMOST_FULL. The memory controller (499) will place therequested address on the memory address bus with the appropriate commandsignals for a WRITE operation. The memory controller (499) also ensuresthat the clock signal 508 (TUNABLE) is set to the correct value. Thememory controller (499) asserts TX POP signal for the duration of theburst. This action moves the data out of the write FIFO (408) onto theexternal memory interface data pins 505. The memory controller (499)manages the POP pointer and maintains internal status of the write FIFO(408) full/empty states. The memory controller (499) will determinewhether a bank has to be precharged, activated early, etc., to ensurethat the dead cycles on the data bus are minimal. If the currenttransaction is the last command in the address FIFO and the user hasasserted PRECHARGE, the memory controller (499) will issue a write withauto precharge for this transaction.

The READ operation is similar to the WRITE operation except that rolesof the PUSH and POP signals are reversed from the perspective of thecontroller and the user. In an example of a read operation, the readFIFO (410) receives data read from the external memory devices usingclock signal (604). The exact sequencing of these operations and theirtiming may be different in different embodiments.

Referring back to FIG. 4, upon power-on, the memory controller (499) isheld in reset and performs no operations. During initialization,memory-specific parameters such as the values for the various counters(e.g., the time delay between a row access strobe and a column accessstrobe represented as t_(RCD)), address width, data width, etc., arewritten into the configuration registers (415) internal to the memorycontroller (499) through a REG_ADDR/WR_DATA interface implemented withmode register data bus (414). This may be accomplished through userlogic (402) external to the memory controller (499). After these initialconfigurations, the memory controller (499) may be further initialized.For example, the user logic (402) may assert STARTINIT and cause thememory controller (499) to perform the initialization sequence. Thememory controller (499) asserts INIT DONE upon the completion of theinitialization sequence. Alternatively, the user logic (402) may performthe initialization sequence by asserting the BYPASS (e.g., BYPASS=1) andcause the memory controller (499) to be in the BYPASS mode. After theinitialization, the user logic (402) may de-assert the BYPASS and causethe memory controller (499) to take over command and control operations.Training sequences may also be implemented through user logic (402), inorder to calibrate one or more memory strobes relative to data. Thecalibration is done before commencing regular transactions. In someembodiments of the present invention, the signals are valid on therising edge of the SYS_CLK.

The memory controller (499) may operate in different modes, includingbut not limited to BYPASS, PRECHARGE, AUTO_REFRESH, POWER DOWN, REFRESH,NOP, ACTIVATE, READ, WRITE, DESELECT, and LD MODE. For example, in theBYPASS mode, the user logic (402) can issue commands directly to theexternal memory devices bypassing the memory controller (499) and theassociated state machines. In the BYPASS mode, bits [51:45] of theAF_DATA [58:0] may take on the roles of RAS#, CAS#, CKE[3:0], WE#/W# andother signals to drive the physical interface with the external memorydevices. Specifically, addresses to the external memory devices arecontrolled through bits [31:12] of the AF_DATA[58:0]. The user logic(402) may control the RX PUSH and TX_POP signals, through bits 56 and57, respectively of the AF_DATA[58:0]. Bit 45 signals a “read” operationif it is set to “0,” and a “write” operation if it is set to “1.” WhenBYPASS=1, the bits of the AF_DATA[58:0] are listed in the followingTable 2.

TABLE 2 List of bits when BYPASS = 1. 58 57 50 55-52 51 55 4P-40 45 4441TX_DQSENABLE TX_POP RX PLISH ODT0[3:01 RAS CAS CKE[3:111 WE CSt3:13]

In normal operations, before the memory controller (499) accesses datathrough read or write commands to a memory bank, a row in that bankneeds to be opened. After a memory bank is opened (e.g., activated), itshould be closed with a “precharge” command before a different row inthe same bank can be opened. In the PRECHARGE mode, in normaloperations, the memory controller (499) will look at the previous, thecurrent, and the next addresses to determine whether the bank and rowneed to be precharged or they should be left open. When the PRECHARGEsignal is enabled, the memory controller (499) uses this information, insituations where the FIFO is either EMPTY or contains the lasttransaction, to issue a precharge. If this signal is disabled, thememory controller (499) leaves the bank and row open for subsequentaccesses. When the AUTO_REFRESH mode is set in the memory controllerconfiguration registers (415), the memory controller (499) automaticallyissues refreshes to the external memory on a fixed period, depending onthe settings in memory controller configuration registers (415). Whenthe POWER DOWN bit is set to 1, the memory controller (499) may managepower of an external memory device automatically. A scenario to managethe power in accordance with some embodiments of the present inventionis described as follows. In an exemplary configuration, a memoryinterface may have a total of four ranks including two 2-Rank DIMMssitting in two slots. A counter for each of the four ranks will count upto a predetermined value set in a delay register. Another bit in thememory controller configuration registers (415) enables or disablespower management. The counters start counting whenever the user setsthis bit. If there are no accesses to a given rank and the counter timesout, the CKE for that rank is pulled low (power down). If there is anaccess to the rank before the counter times out, the counter is resetand the cycle continues. When the REFRESH bit is set to 1, the memorycontroller (499) issues a refresh to the external memory immediatelyafter completing the current transaction.

The LD_MODE allows the user to update the mode register settings in thememory controller configuration registers (415). When enabled, thememory controller (499) completes the current set of transactions andloads the mode register settings into the external memory. The MRS_DONEsignal is asserted when the controller completes the load. A dedicatedinterface may be provided to the user to write or read the informationin the memory controller configuration registers (415). Theconfiguration registers (415) will hold information regarding the moderegister settings, including various timing parameters such as ACTIVATETO READ/WRITE delay, etc. The configuration registers (415) will containdefault settings at configuration. The user can override the defaultsettings by writing to registers using REG_ADDR, REG_WDATA, and REG_WEsignals. Data from these registers may also be read back using theseinterfaces. Some operation modes such as AUTO_REFRESH may optionally betreated as a register setting instead of a user input from a separatepin.

The register map for the memory controller is shown in the followingTable 3.

TABLE 3 Register map for an exemplary memory controller. LocationComments 0, 1, 2 DDR/RLDRAM MRS 3, 4, 5 DDR EMRS1 6, 7, 8 DDR EMRS2 9,10, 11 DDR EMRS3 12 <4:0> CONFIG- Memory type (see below table) 13 <4:0>CONFIG- Address width 14 <6:0> CONFIG- Data width 15 <2:0> QDR BurstLength configuration 16 Data Path Delay configuration (tx 1:0, rx 5:4)17 <1:0> Ts_en path delay configuration 18 <4:0> Sdr to ddr clock phaseselect- 32 taps 19 <4:0> Ddr to sdr clock phase select- 32 taps 20Read/Write Data FIFO threshold configuration tx <3:0>, rx<7:4> 21 RLD2mrs configuration 22 <7:5> row config, <4:2> column config, <1:0> bankconfig 23 DDR Refresh done LSB count (sm_sel = 1) - duringinitialization 24 DDR Refresh done LSB count (sm_sel = 2) - duringinitialization 25 DDR Refresh done MSB count (sm_sel = 1) - duringinitialization 26 DDR Refresh done MSB count (sm_sel = 2) - duringinitialization 27 RLD Refresh done LSB count (sm_sel = 3) - duringinitialization 28 RLD Refresh done LSB count (sm_sel = 0) - duringinitialization 29 RLD Refresh done MSB count (sm_sel = 0) - duringinitialization 30 RLD Refresh done LSB count (sm_sel = 1.2) - duringinitialization 31 RLD Refresh done MSB count (sm_sel = 1.2) - duringinitialization 32 <3:0> DDR cntr 0 done value 33 <3:0> DDR cntr 1 donevalue 34 <3:0> DDR cntr 2 done value 35 <3:0> DDR cntr 3 done value 36<3:0> DDR cntr 4 done value 37 <3:0> DDR cntr 5 done value 38 <3:0> DDRcntr 6 done value 39 <3:0> DDR cntr 7 done value 40 <3:0> DDR cntr 8done value 41 <3:0> DDR cntr 9 done value 42 <3:0> DDR cntr 10 donevalue 43 <4:0> DDR cntr 11 done value 44 <5:0> DDR cntr 12 done value 45<5:0> DDR cntr 13 done value 46 DDR Refresh done = LSB count (sm_sel =0)- during/after initialization 47 DDR Refresh done = MSB count (sm_sel= 0)- during/after initialization 48 <3:0> RLD cntr 0 done value 49<3:0> RLD cntr 1 done value (Bank 0 counter) 50 <3:0> RLD cntr 2 donevalue (Bank 1 counter) 51 <3:0> RLD cntr 3 done value (Bank 2 counter)52 <3:0> RLD cntr 4 done value (Bank 3 counter) 53 <3:0> RLD cntr 5 donevalue (Bank 4 counter) 54 <3:0> RLD cntr 6 done value (Bank 5 counter)55 <3:0> RLD cntr 7 done value (Bank 6 counter) 56 <3:0> RLD cntr 8 donevalue (Bank 7 counter) 57 <3:0> RLD cntr 9 done value (Write latencycounter) 58 <3:0> RLD cntr 10 done value 59 <4:0> RLD cntr 11 done value60 <5:0> RLD cntr 12 done value 61 <5:0> RLD cntr 13 done value 62 RLDRefresh done LSB count after initialization 63 RLD Refresh done MSBcount after initialization Memory Type MT_DDR 5′b0_0001 MT_DDR25′b0_0010 MT_DDR3 5′b0_0011 MT_DDR_UD 5′b0_0100 MT_DDR_RD 5′b0_0101MT_DDR2_UD 5′b0_0110 MT_DDR2_RD 5′b0_0111 MT_RLD1_X32 5′b0_1000MT_RLD1_X16 5′b0_1001 MT_RLD_II 5′b0_1010 MT_RLD_II_SIO 5′b0_1011MT_QDR_DDR_X18 5′b0_1100 MT_QDR_DDR_X36 5′b0_1101 MT_QDR_DDR_X85′b0_1110 MT_QDR_DDR_X9 5′b0_1111 MT_QDR2_X18 5′b1_0000 MT_QDR2_X365′b1_0001 MT_QDR2_X8 5′b1_0010 MT_QDR2_X9 5′b1_0011 MT_QDR_X18 5′b1_0100MT_QDR_X36 5′b1_0101 ADDR DATA 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0x01 ModeRegister 0 0x02 Mode Register 0 0x03 Mode Register 0 0x04 Mode Register1 0x05 Mode Register 1 0x06 Mode Register 1 0x07 Mode Register 2 0x08Mode Register 2 0x09 Mode Register 2 0x0A Mode Register 3 0x0B ModeRegister 3 0x0C Mode Register 3

Referring to FIG. 7, information in the configuration register (415) maybe used by the state machines (such as initialization (706), moderegister set (708), refresh (710), add & control (712), read (714), andwrite (716)). For example, the state machine refresh (710) may use thememory type settings to determine the required refresh rate for theexternal memory devices. In an example, configuration register (415),initialization (706), mode register set (708), refresh (710), add &control (712), read (714), and write (716) are preferably implementedusing hard macros. The delay calibration (704) and clock generation(702) may be implemented as soft macros. Exemplary burst definitionswith burst lengths of 4 and 8 are listed in the following Table 4.

TABLE 4 Burst definition. Starting Column Order of Accesses Within aBurst Burst Address Burst Type = Burst Type = Length (A2, A1, A0)Sequential Interleaved 4 00 0, 1, 2, 3 0, 1, 2, 3 01 1, 2, 3, 0 1, 0, 3,2 10 2, 3, 0, 1 2, 3, 0, 1 11 3, 0, 1, 2 3, 2, 1, 0 8 000 0, 1, 2, 3, 4,5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5,4, 7, 6 010 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 011 3, 0, 1,2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6,7, 0, 1, 2, 3 101 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 110 6,7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 111 7, 4, 5, 6, 3, 0, 1, 2 7,6, 5, 4, 3, 2, 10

Examples of address mapping schemes include RA:BA:ROW:COL andROW:RA:BA:COL. A length field may be additionally included to indicatehow many bursts are to be accessed from the external memory. A burstlength may be programmed by the user and specified in the length field.The memory controller (499) breaks up the access into multiple DDRbursts based on the programmed burst length, bus width, and startaddress alignment. Adding the access length field to the Address FIFOallows for more efficient use of the FIFO. It also allows the memorycontroller (499) to access the next entry in the FIFO and start thisaccess as soon as possible, thereby facilitating overlapping ofcommands.

Memory command overlapping increases memory efficiency, and allowsdelays for transactions such as active to read/write (t_(RCD)) andread/write precharge (t_(RpD)) to be hidden for subsequent sequentialaccess to memory. A second bank or command register is added to pop thenext entry in the Address FIFO. Comparison logic will be necessary todecide whether this next command will access the same bank, the samepage, or a new bank, etc. When a command is written into the AddressFIFO it will be read by the memory controller (499) as soon as possible.The memory controller (499) will activate the bank associated with thiscommand's address. If there is a second entry in the Address FIFO, it isread from the FIFO immediately after the first. If the second command'saddress is in another bank, that bank will be activated as soon asallowed by the DDR memory and as soon as there is an available slot onthe memory bus (the DDR command bus is idle). If the first command'saccess to memory is longer than the time it takes to activate the secondcommand's bank (_(tRcD))_(,) access to the second command's data canstart immediately upon completing the first command's access, therebyhiding the entire activation of the second bank. After a command hascompleted accessing memory, the decision to precharge will be based onthe next command. If the next command is in the same page, prechargewill not be necessary. If the next command requires a new bank, theprevious bank will be precharged and the new bank activated. The goal isfor the precharge and new bank activation to be completed while data isbeing transferred for the most current operation.

The memory controller in accordance with an embodiment of the presentinvention expects aligned addresses, and unaligned addresses are handledthrough logic external to the memory controller. Consider an example ofa 64-bit DDR memory configured for a burst length of 4, length field isset to 1 burst. If a user requests a read at address x000, the memorycontroller issues a single read, and the memory returns 4×8 Byte ofdata. Each 8 Byte data chunk is read from the DDR internal memorylocations 0, 1, 2, and 3 in that order. On a subsequent read, the nextaligned address the user should use is x004, which is an integermultiplication of the burst length. Consider an example of a non-alignedaddress, address=x002. If the controller issues a read to this address,the memory will return 4×8 Bytes of data from the internal locations 2,3, 0, 1 in that order. If there are no more entries in the FIFO, thememory controller does not issue RX_PUSH to the DGPIO. In the writecase, the controller issues an interrupting command when applicable toprevent wasted cycles of writing masked data. If interrupting a writecommand, the memory controller will mask the extra write cycles.

Read modify write (RMW) cycles are needed when an agent writes a partialword to memory and when ECC is turned on. A wrapper may be used in thecase that the memory controller does not support RMW. Thus, the need foran RMW cycle must be calculated before the command is put into theAddress FIFO. If an RMW cycle is needed, the wrapper will break theoriginal write command into an individual read and a write. Once theread is issued, no other command is put into the Address FIFO until theread data is returned, the original write data and read data are mixed,new ECC is calculated and the data/ECC are written back to memory.

The memory controller (499) in accordance with some embodiments of thepresent invention is adapted to manage power consumption in externalmemories. Power management is enabled or disabled using one bit in thememory controller configuration registers (415). For example, consider acase with a memory interface having two 2-Rank DIMMs sitting in twoslots, and thus the interface has four ranks in total. A programmabledelay is provided for each rank. A counter for each rank starts countingup to a value set in the delay register whenever the user enables thepower management. If there are no accesses to a rank and thecorresponding counter times out, the rank is powered down by pulling lowa CKE. If there is an access to the rank before the counter times out,the counter resets and the cycle continues.

A number of soft cores may be provided to supplement the functionalitiesof the memory controller (499), such as training pattern generator, DQSpreamble and post amble generator, read external ROM and load registermap, RMW logic, user FIFO logic for clock domain conversion, non-alignedto aligned address mapping, etc.

FIG. 8 shows an exemplary design and programming system for theheterogeneous configurable integrated circuit (200). Here, system (800)includes HDL design (802), Module Libraries (804), Synthesis Tools(806), Physical Implementation Tools (808), Analysis Tools (810), andConfiguration Tools (812). A design may be entered in hardwaredescription language (HDL) in the form of an HDL design (802). The HDLmay include: Verilog, VHDL, System Verilog, or any combination there of.Module Libraries (804) may include a number of models representingspecial-purpose blocks, such as a model for the memory controller (499).The HDL design (802) may infer, or include by reference, the memorycontroller model or other models from the Module Libraries (804)according to the functions required by the design. The Synthesis Tools(806) may map the design to be composed of PLB functionalities and thememory controller model or other models corresponding to the designfunctions. The Physical Implementation Tools (808) may perform placementof the PLB functionalities and the memory controller model or othermodels onto the PLB fabric and the corresponding special-purpose blocks.The Physical Implementation Tools (808) may further perform routing ofthe PLB fabric and the memory controller or other special-purpose blocksto complete the implementation of the design. The Analysis Tools (810)may analyze timing delays and interconnection latency of the designimplementation. The Configuration Tools (812) may prepare configurationinformation and perform the configuration of the heterogeneousconfigurable integrated circuit (200) according to the completed designimplementation. In embodiments of the invention, the memory controllermodel from the Module Libraries (804) may include information relatingto signal nodes, such as AF DATA, or the like) suitable for connectingusing the high speed communications fabric of the heterogeneousconfigurable integrated circuit (200). This information may be utilizedby the Physical Implementation Tools (808) to perform routing using theinterconnect stations (202) of the reconfigurable high speedcommunications fabric. The memory controller model from the ModuleLibraries (804) may also include information relating to certain circuitrequirement, (such as multiple signals requiring matched interconnectlatency) to accommodate the latency associated with the pipelined buses.This information may be utilized by the Synthesis Tools (806) to performthe design mapping according to the circuit requirement. The AnalysisTools (810) may provide information relating to delay timing violationor interconnection latency violation of the completed designimplementation with respect to design requirement. This information maybe utilized by the Synthesis Tools (806) and the Physical ImplementationTools (808) to fine tune the design mapping and placement routing in adesign iteration. For example, the design mapping and placement routingmay be fine tuned as shown in the descriptions relating to FIG. 3A and3B. Further, the Analysis Tools (810) may provide information relatingto estimated interconnection clock frequency and latency prior to theSynthesis Tools (806) performing design mapping or the PhysicalImplementation Tools (808) performing placement routing. Thisinformation may be utilized by the Synthesis Tools (806) or the PhysicalImplementation Tools (808) to execute timing driven or latency drivenalgorithms for optimizing the design implementation with reduced designiterations.

Applications of the memory controller for the heterogeneous configurableintegrated circuit in accordance with embodiments of the presentinvention include, but are not limited to, network and storageswitching/routing, broadband aggregation, security and contentinspection, optical transport, telecom, wireless base station, NPUoffload packet acceleration, and layer 4-7 applications.

Advantages of one or more embodiments of the present invention mayinclude, but are not limited to: separate data and control paths allowthe capability of re-allocating resources; improved system performanceand lower power consumption; distributed data bits and commandoverlapping; capable of assigning pins thus increasing systemflexibility.

Advantages of one or more embodiments of the present invention include amemory controller that can be reconfigured for use with a large varietyof external memory technologies, and their corresponding burst sizes,read-write latencies, bus widths, bank sizes, and clock frequencies.Further, the memory controller may be reconfigured with minimal changeto the rest of the system.

While the invention has been described with respect to a limited numberof embodiments, those skilled in the art, having benefit of thisdisclosure, will appreciate that other embodiments can be advised whichdo not depart from the scope of the invention as disclosed herein.Accordingly, the scope of the invention should be limited only by theattached claims.

What is claimed is:
 1. A method for routing data in a configurableintegrated circuit, comprising: programming a plurality of interconnectstations into a station mesh for high speed data transfer; configuring aplurality of programmable logic blocks (“PLBs”) into a PLB array meshfor performing logic functions; programming a plurality of pipelinedbuses between the station mesh to facilitate high speed data transferbetween the interconnect stations; and selectively linking at least aportion of the plurality of interconnect stations to a portion of theplurality of PLB s to merge the station mesh into the PLB array mesh toform a high speed communications fabric.
 2. The method of claim 1,further comprising programming a portion of the plurality of PLBs toperform a function of memory control.
 3. The method of claim 1, furthercomprising configuring a special purpose block into the high speedcommunications fabric.
 4. The method of claim 1, wherein programming aplurality of interconnect stations into a station mesh includesarranging interconnect stations in an array configuration.
 5. The methodof claim 4, wherein arranging interconnect stations includes allowingeach interconnect station having at least two neighboring interconnectstations.
 6. The method of claim 1, wherein configuring a plurality ofPLBs into a PLB array mesh includes arranging PLBs in a logical arrayconfiguration separated by at least one interconnect station.
 7. Themethod of claim 6, wherein arranging PLBs in a logical arrayconfiguration includes allowing each PLB having at least one connectionto a neighboring interconnect station.
 8. The method of claim 1, whereinprogramming a plurality of pipelined buses between the station meshincludes configuring connectivity of a least portion of the pipelinedbuses in accordance with values stored in a configuration register. 9.The method of claim 1, wherein selectively linking at least a portion ofthe plurality of interconnect stations to a portion of the plurality ofPLBs includes configuring connectivity between at least a portion of theinterconnect stations and a portion of PLBs in accordance with valuesstored in a configuration register.
 10. The method of claim 1, whereinprogramming a plurality of pipelined buses between the station meshincludes coupling an output ramp of a first interconnect station to aninput ramp of a second interconnect station via a pipelined bus.
 11. Themethod of claim 1, wherein selectively linking at least a portion of theplurality of interconnect stations to a portion of the plurality of PLBsincludes coupling an output port of a first interconnect station to aninput port of a PLB for facilitating performance of a logic function.12. A configurable integrated circuit, comprising: a plurality ofinterconnect stations configured to programmably couple to a stationmesh for high speed data transfer; a plurality of programmable logicblocks (“PLBs”) coupled to the plurality of interconnect stations andconfigured into a PLB array mesh for performing logic functions; aplurality of pipelined buses between the station mesh capable of beingprogrammed to facilitate high speed data transfer between theinterconnect stations; and a portion of the plurality of interconnectstations coupled to the plurality of interconnect station and configuredto selectively link to a portion of the plurality of PLBs to merge thestation mesh into the PLB array mesh to form a high speed communicationsfabric.
 13. The circuit of claim 12, wherein a portion of the pluralityof PLBs is programmed to perform a function of memory control.
 14. Thecircuit of claim 12, further comprising a special purpose blockconfigured to facilitate managing the high speed communications fabric.15. The circuit of claim 12, wherein the plurality of interconnectstations into a station mesh is arranged in an array configuration. 16.The circuit of claim 13, wherein arranging interconnect stationsincludes allowing each interconnect station having at least twoneighboring interconnect stations.
 17. The circuit of claim 12, whereinat least a portion of the plurality of PLBs is separated by at least oneinterconnect station.
 18. The method of claim 17, wherein each of theplurality of PLBs has at least one connection to a neighboringinterconnect station.
 19. A method for routing data in a configurableintegrated circuit, comprising: programming a plurality of interconnectstations into a station mesh for high speed data transfer; configuring aplurality of programmable logic blocks (“PLBs”) into a PLB array meshfor performing logic functions; programming a plurality of pipelinedbuses between the station mesh to facilitate high speed data transferbetween the interconnect stations; selectively linking at least aportion of the plurality of interconnect stations to a portion of theplurality of PLB s to merge the station mesh into the PLB array mesh toform a high speed communications fabric; and setting values in aconfiguration register via a dedicated interface.
 20. The method ofclaim 1, further comprising: programming a portion of the plurality ofPLBs to perform a function of memory control; and configuring a specialpurpose block into the high speed communications fabric.